D K Bhargav Achary · Pune, India
Understanding performance, from silicon to systems.
I’m Bhargav, a computer architecture and performance engineer. I connect what a workload needs with what the processor, cache and memory system actually do.
My experience spans IBM Power, AMD Ryzen and Qualcomm Hexagon DSP: C/C++ performance models, workload characterisation, PMU analysis and simulator-to-RTL correlation.
- The workloadWhat useful work needs to happen?
- The processorHow does the core execute it?
- Cache & memoryWhere does the data wait?
- Measurement & modelsDoes the explanation fit the evidence?
Trace the behaviour. Test the explanation.
Architecture & modelling
Processor behaviour, cache coherence, memory hierarchies and interconnects, connected through simulation and measurement.
Performance investigation
Workload characterisation and PMU analysis to find bottlenecks and test whether a proposed explanation fits the evidence.
Hardware meets software
Exploring DNN workloads, on-device inference and the engineering workflows that make complex systems easier to reason about.
Learning from hardware counters
My IIT Hyderabad research used hardware performance counters and machine learning to infer DNN layer types, leading to an ACM AIMLSystems ’21 publication.
Research and independent projectsPerformance Analysis 101
A practical starting point for understanding why fast specifications do not always produce a responsive experience.
Why a Fast Computer Can Still Feel SlowWhy a Fast Computer Can Still Feel Slow
Performance Analysis 101, Part 1: understanding latency, critical paths, and why low CPU utilisation or high average FPS can leave the real delay unexplained.
Beyond the Chat Window: AI Agents, Work, and the Individual Engineer
Configuring my Nikon Z6 with AI, a solo Bobathon win, and Apple's Gemini turn: what agents make possible, and where judgment, privacy, and cost still matter.
NVLink Fusion: NVIDIA's Bold Step Towards Unified AI Memory Architectures
NVIDIA's NVLink Fusion revolutionizes AI computing by creating unified memory architectures that eliminate CPU-GPU data transfer bottlenecks, enabling direct memory sharing for breakthrough performance in large language models and scientific computing.
Have an interesting systems problem?
I welcome conversations about engineering roles, technical collaboration, speaking and consulting enquiries.